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Instruction recall

memory
control-flow
Instruction cache invalidation and multibyte operation reconstruction.
Published

December 1, 2024

If a cache miss happened in the middle of a multi-byte instruction, the instruction and all subsequently fetched bytes are immediately marked as invalid. The processor jumps to redo the instruction depending on the parent byte of a multi-byte instruction and which byte was invalid once the invalidation has been resolved.

fetch fetch decode decode execute writeback
mst invalidated
low byte invalidated
high byte, cache miss cache miss known invalidated