Instruction recall

Instruction cache invalidation and multibyte operation reconstruction.

If a cache miss happened in the middle of a multi-byte instruction, the instruction and all subsequently fetched bytes are immediately marked as invalid. The processor jumps to redo the instruction depending on the parent byte of a multi-byte instruction and which byte was invalid once the invalidation has been resolved.

fetch	fetch	decode	decode	execute	writeback
mst					invalidated
low byte					invalidated
high byte, cache miss	cache miss known				invalidated

1 Instruction pointer sources

• 16 bit incremented fetch address (default, pc + 1)
• 16 bit absolute address (jmp)
• 8 bit relative address, addition with source address (jmpr, brh)
• 16 bit dynamic absolute address (jmpd)
• 16 bit incremented source address (branch recovery for brh)
• 16 bit return address from stack/memory
• 3, 16 bit addresses from boot page (entrypoint addr., interrupt addr., kernel addr.?)
• 3, 16 bit instruction recall addresses for source, source - 1, source - 2