Introduction to QCPU 2

An introduction into the QCPU 2 architecture and its assembly language.
Published

October 9, 2025

QCPU 2 is a 16 bit instruction, 16 bit data, 16 bit address microprocessor architecture. The CPU may run in a symmetric configuration using its hart (hardware thread) identification, similar to RISC-V harts. That being said, QCPU 2 is heavily based on the RISC-V design, tailored to a more real-time specification.

1 General Purpose Registers

There are eight operand-addressable General Purpose Registers (GPRs):

  • r0: zr (zero read, void write)
  • r1: rp (return pointer)
  • r2: sp (stack pointer)
  • r3: x1 (argument 1/return)
  • r4: x2 (argument 2/return)
  • r5: x3 (argument 3/return)
  • r6: t1 (temporary)
  • r7: t2 (temporary)

Contrary to their name, rp and sp don’t include special logic (however, the jump-and-link family of instructions do write to rp on link). It’s conventional to use r2/sp as the pointer to a stack in memory. Realistically, there are five available registers to perform general-purpose operations with, before having to spill data to memory (like a stack).

2 Special Purpose Registers

There are two non-addressable Special Purpose Registers (SPRs):

  • ip (instruction ptr)
  • fl (flag register)

The instruction pointer is incremented every cycle, except on jump-like instructions, which set the instruction pointer to a resolved address. The flag register is written to every ALU or barrel shifter operation.

Both SPRs can be read from directly through the Control & Status Register (CSR) instructions. The flag register can be written to in kernel mode, but the instruction pointer can not.

3 Memory

QCPU is a RISC-like, load-store architecture. There’s a family of mst (memory store) and mld (memory load) instructions. Each memory instruction has an associated instruction to operate on words (the full 16 bit register).

Memory accesses are asynchronous. If a read happens to a destination register, the GPR’s async resolved bit is reset. A read operation on that register stalls the CPU when the async operation is not yet resolved. Memory writes are queued in the same way, but can only be awaited using the fence pseudoinstruction. Atomic instructions (xch family of instructions) are also async, but atomic with symmetric multiprocessing.

4 Assembly language

QCPU 2 has an assembly language toolchain.