Introduction to QCPU 2
QCPU 2 is a singular operand architecture, which means its instructions can be 8 bits in size. Its address space, however, is 16 bits. There are certain instructions which take an additional one or two bytes for instructions.
1 Register map
- Accumulator:
ra(0) - Zero register:
zr(0) - General purpose:
rb,rc,rd,re(1-4) - Subroutine args:
rx,ry,rz(5-7)
1.1 Special registers
There are a couple of special, non-addressable registers:
- Stack pointer:
sp(u16) - Stack frame pointer:
sf(u16)
1.2 Async memory registers
Memory can be fetched from asynchronously, using the amr* instructions, and read from through the amr instruction. Pending registers (those who have called for a fetch, but not yet received a response) will cause the processor to stall. The addressable registers are:
- A:
mah,mal - B:
mbh,mbl - C:
mch,mcl - D:
mdh,mdl
1.3 Index register
Certain memory operations can use registers rx and ry as the 16 bit index register, as opposed to either one of the special registers or none. See the memory chapter for more information about memory accessing and data flow.