Introduction to QCPU 2
QCPU 2 is a 16 bit instruction, 16 bit data, 16 bit address microprocessor architecture.
1 General-purpose registers
The QCPU 2 architecture implements Data Registers (DRs) as well as Address Registers (ARs). A distinction is made between these two types to encode more general-purpose registers into the architecture. This is a concept seen in the Motorola 68000.
Instructions are more likely to allow access to DRs than ARs, but ARs provide a couple of special properties. In QCPU 2, some ARs are specially mapped in the microprocessor, such as the instruction pointer, which replaces necessary jump instructions with regular move and add operations with the addressable instruction pointer register. Likewise, the return pointer is written to during jump-and-link instructions. In general, ARs can emit hardware exceptions on over-/underflows during arithmetic operations.
+- Data Registers -+ +- Address Registers -+
| | | |
| Fully General | | Partially General |
| Purpose | | Purpose |
| | | |
| r0 zero | | r8 zero |
| r1 d1 | | r9 instruction ptr |
| r2 d2 | | r10 return ptr |
| r3 d3 | | r11 stack ptr |
| r4 d4 | | r12 frame ptr |
| r5 d5 | | r13 a1 |
| r6 d6 | | r14 a2 |
| r7 d7 | | a15 a3 |
| | | |
+---------------------+ +---------------------+
Addition Addition
Addition with imm. Addition with imm.
Comparison with imm. -
Move conditionally Move conditionally
Subtraction Subtraction
Set conditionally -
Bitwise -
Barrel shift -
Load imm. Load imm.
Memory source/dest. -
- Memory address
- Predec./postinc.
- Over-/underflow exc.2 Control & Status Registers
Control & Status Registers (CSRs) are microprocessor extensions to read system information and configure the system. They can only be accessed in kernel mode through the csrr and csrw instructions, which reads a CSR to and writes to a CSR from a DR, respectively.
In kernel start-up, the most important CSRs are reading the hart (hardware thread) and configuring the ft (system features). These features configure memory synchronicity, the Branch Target Buffer (BTB), kernel protection, interrupts, and so on. Similarly, internal system registers can be read from and written to through the use of CSRs, such as the flag register, the stack low/high limit, and the microprocessor time interrupter. A general-purpose scratch register is present in the CSRs for use in interrupt context switches.
3 Instruction encoding
The Instruction Set Architecture (ISA) of QCPU 2 use fixed-length instructions. The encoding contains up to three register operands. In all instructions, a 5 bit operation code (opcode) is present. A function code is present in a subset of the instructions. A basic instruction with two sources and a destination is encoded as:
| opcode | dest | fn | src 1 | src 2 |
result-type | X X X X X | R R R | Y Y | R R R | R R R | ALU operations
| 15 11 | 10 8 | 7 6 | 5 3 | 2 0 |
| MSB LSB |Similarly, the following other instruction encodings are available:
| opcode | immediate | reg |
immediate-type | X X X X X | I I I I I I I I | R R R | ALU/load operations
| |
| opcode | immediate |
full immediate-type | X X X X X | I I I I I I I I I I I | Jump and link operations
| |
| opcode | shift | src | dest |
barrel-type | X X X X X | Y I I I I | R R R | R R R | Barrel shifter operations
| |
| opcode | offset | addr. | reg |
memory static-type | X X X X X | I I I I I | R R R | R R R | Memory move operations
| |
| opcode | id | fn | id | reg |
id-type | X X X X X | I I I | Y Y | I I I | R R R | System calls/CSR operationsNotation legend:
X: 5 bit operation codeY: subfunction of opcodeI: immediate value (optionally sign extended, depending on opcode)R: source, destination, writeback location, subfunction, or condition code, depending on opcode
These six total instruction encodings provide the baseline for the decode stage of the QCPU 2 microprocessor. It is implemented as such that register source operands have a fixed location in the instruction encoding. Contrarily, the destination operand is either located in bits 10…8 or 2…0. A condition code is always located in bits 2…0.
Instructions can be classified as working with word (16 bit) registers rather than byte (8 bit) registers. For example, memory move operations can be done with move (lower register byte) or with movew (full register word). With immediate operands, these word-based instructions align the immediate by 2. As such, the byte reach of the immediate is doubled. For example, move’s 5 bit signed immediate is ranged -16…15 bytes, whilst movew’s 5 bit signed immediate is ranged -32…31 bytes, but aligned by 2. In a special case, immediate operations with the destination of the instruction pointer or return pointer also provide this aligned-by-2 functionality.
4 Assembly language
QCPU 2 has an assembly language toolchain.