Boot process

A CPU’s first steps and different execution modes.

Similarly to x86’s unprotected and protected control modes, QCPU is able to run in two different execution modes: direct and exec [1]. A ‘direct’ execution mode turns off the virtual memory system and starts up differently than the ‘exec’ mode. Each have their benefit. For simple, non-operating system programs, the ‘direct’ execution mode can be used to remove the overhead of loading in the kernel, reduce the response time of the program, amongst other tasks [2, Ch. 3.1].

1 Physical memory layout

Section ‘I/O’ of the ‘Physical devices’ chapter mentions the initial physical memory pages that are used by the configuration. There are 24 total pages mapped to I/O devices, which are all 256 byte register files to communicate with their respective devices. The 232 rest pages are managed by the main memory port [3, Ch. 3].

Two built-in I/O devices are present in the QCPU microcontroller’s physical memory:

• Boot sector ROM device [0] (processor/kernel control block),
• DMAC device [1] (interaction points with hardware).

0       1      2              23 24                 255
[ boot | dmac | ... devices ... | ... main memory ... ]
               v   v             v
example:       tty storage       kernel
                   controller

¹

The start-up content and behaviour of the ‘boot’ sector device differs between the two processor execution modes explained in both Section 1.1 and Section 1.2.

1.1 Execution mode: ‘direct’

In direct mode, the virtual memory system maps each address to the same physical memory address. Kernel mode restrictions are disabled. The virtual memory essentially functions as a ‘linear’ address map compared to the three-step map process (kfixed, kvariable and userland).

1.2 Execution mode: ‘exec’

In exec mode, upon booting, the microcontroller loads physical page zero at the kfixed region and jumps to the entrypoint given in the control block (which is the ‘boot’ sector device). The CPU begins in kernel mode. An entrypoint program (like a bootloader, to later expand to a kernel when it’s loaded from a persistent storage device) is expected to be loaded at the address of the entrypoint.

1.3 Process/CPU Control Block

A ‘control’ block registers which addresses to use for the processor as well as parameters for a userspace application. Like an entrypoint address, they configure QCPU’s runtime. Typically, in exec mode, the control block is also used for userland sections.

On reset, QCPU jumps to the entrypoint address given in the boot sector (and freshly loads it from physical memory section 0 on rising edge).

• Entrypoint addr. [0, 1],
• Interrupt addr. [2, 3],
• Reserved addr. [4, 5],
• Processor flags [6, 7].

Userspace:

• Begin stack [8, 9]
  • Current stack frame [10, 11]
  • Current stack pointer [12, 13]

Note that these values aren’t 1:1 with the special registers for the stack frame/pointer, and are instead ideally to be set by the kernel when switching userland processes.

Processor flags (for boot sector, LSB first):

• Memory virtualisation enabled (exec mode),
• Interrupts enabled,
• Branch Target Buffer enabled,
• Branch Target Identification enabled.

References

[1]

“Memory access control method and system for realizing the same” Available: https://web.archive.org/web/20070926220520/http://www.patentstorm.us/patents/5483646-claims.html

[2]

Intel 64 and IA-32 architectures software developer’s manual volume 1: Basic architecture. Intel, 2019. Available: https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-software-developers-manual-volume-1-basic-architecture

[3]

Memory management. arm, 2019. Available: https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/LearnTheArchitecture-MemoryManagement-101811_0100_00_en.pdf?revision=01a01804-ca64-4e19-a55e-2af56afea5a5

Footnotes

1. Storage controller may be integrated into the ‘DMAC’ device for memory references