CSRs

Control & Status Registers

CSRs are only available in kernel mode. They provide system-specific extensions to the microprocessor, and can be read from and written to with the csrr and csrw instructions, respectively, providing a 6 bit address with a total of 64 CSRs. A write to a read-only CSR results in a nop. Reads have no side-effect, and reads into the zr void register are therefore implemented as zero-operand instructions in the ISA.

Address	Short	Privilege	Length	Description	Caveats
0x000	misa	RO	16	Machine ISA	constant by implementation
0x000	ft *	RW ***	16	Features	prot, btb, async, interrupts
0x000	hart **	RO	16	Hardware thread	constant by implementation
0x000	fr	RW	4	Flag register	carry, half carry, sign, zero
0x000	int	RO	8	Interrupt id	written by interrupt
0x000	ival	RO	16	Interrupt value	written by interrupt, e.g. memory address
0x000	irp	RW	16a2	Interrupt return ptr	written by interrupt and kernel, used by reti
0x000	imsk	RW	1	Interrupt mask	written by interrupt, one if pending (mask)
0x000	vec	RW ***	16a2	Interrupt vector	interrupt jump location (irp kernel mode region)
0x000	ien *	RW ***	16	Interrupt enable register	timer, sysc, addr., mem, …
0x000	scr	RW	16	Scratch register	used by e.g. interrupt context switches
0x000	ctb	RW ***	8	Time base clock	clock timer prescale
0x000	itb	RW ***	8	Time base interrupt	interrupt timer prescale
0x000	prfi	WO	16	Prefetch instruction	prefetches instruction memory
0x000	spl	WO	16	Stack pointer low limit	destination sp low limit
0x000	sph	WO	16	Stack pointer high limit	destination sp high limit

* Guaranteed 0 on reset.

** Guaranteed hart 0 to exist in any system configuration.

*** Subject to change: RW -> WO.

TODO: virtual memory configuration CSRs